LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY test0002 IS
  PORT(
    BUTTON  : IN std_logic;
    LED1_A  : out std_logic;
    LED1_B  : out std_logic;
    LED1_C  : out std_logic;
    LED1_D  : out std_logic;
    LED1_E  : out std_logic;
    LED1_F  : out std_logic;
    LED1_G  : out std_logic
  );
END test0002;

ARCHITECTURE rtl of test0002 IS
  COMPONENT TEST7492
  PORT(
    CLK : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic
  );
  END COMPONENT;
  COMPONENT TEST7442
  PORT(
    IN_A  : IN std_logic;
    IN_B  : IN std_logic;
    IN_C  : IN std_logic;
    IN_D  : IN std_logic;
    LED_A : out std_logic;
    LED_B : out std_logic;
    LED_C : out std_logic;
    LED_D : out std_logic;
    LED_E : out std_logic;
    LED_F : out std_logic;
    LED_G : out std_logic
  );
  END COMPONENT;
SIGNAL LA : std_logic;
SIGNAL LB : std_logic;
SIGNAL LC : std_logic;
SIGNAL LD : std_logic;

BEGIN

  cnt : TEST7492 port map(
    CLK => BUTTON,
    QA  => LA,
    QB  => LB,
    QC  => LC,
    QD  => LD
  );
  dec : TEST7442 port map(
    IN_A => LA,
    IN_B => LB,
    IN_C => LC,
    IN_D => LD,
    LED_A  => LED1_A,
    LED_B  => LED1_B,
    LED_C  => LED1_C,
    LED_D  => LED1_D,
    LED_E  => LED1_E,
    LED_F  => LED1_F,
    LED_G  => LED1_G
  );
END rtl;