-----------------------------------------------------------------------
-- 6進カウンタサンプル
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

ENTITY TEST7492 IS
  PORT(
    CLK : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic
    );
END TEST7492;

ARCHITECTURE rtl of TEST7492 IS
  SIGNAL counter : std_logic_vector(3 downto 0);
BEGIN

  PROCESS(CLK)
  BEGIN
    if(CLK'event and CLK='1') then

      if( counter = 5 ) then
        -- カウンタの値が6まで増えてしまったときは0に戻す
        counter <= CONV_STD_LOGIC_VECTOR(0,4);
      else
        -- それ以外のときは1増やす
        counter <= counter + 1;
      end if;
    end if;
  END PROCESS;

  -- カウンタレジスタの各ビットをQAからQDに出力します
  QA <= counter(0);
  QB <= counter(1);
  QC <= counter(2);
  QD <= counter(3);
end rtl;