----------------------------------------------------------------------- -- サイコロデコーダサンプル ----------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY TEST7442 IS PORT( IN_A : IN std_logic; IN_B : IN std_logic; IN_C : IN std_logic; IN_D : IN std_logic; LED_A : out std_logic; LED_B : out std_logic; LED_C : out std_logic; LED_D : out std_logic; LED_E : out std_logic; LED_F : out std_logic; LED_G : out std_logic ); END TEST7442; ARCHITECTURE rtl of TEST7442 IS SIGNAL number : std_logic_vector(3 downto 0); BEGIN -- numberの0ビット目はA number(0) <= IN_A; -- numberの1ビット目はB number(1) <= IN_B; -- numberの2ビット目はC number(2) <= IN_C; -- numberの3ビット目はD number(3) <= IN_D; LED_A <= '1' when number = 0 else '0' when number = 1 else '1' when number = 2 else '0' when number = 3 else '1' when number = 4 else '0' when number = 5 else '1'; LED_B <= '0' when number = 0 else '1' when number = 1 else '0' when number = 2 else '1' when number = 3 else '1' when number = 4 else '1' when number = 5 else '1'; LED_C <= '0' when number = 0 else '1' when number = 1 else '0' when number = 2 else '1' when number = 3 else '1' when number = 4 else '1' when number = 5 else '1'; LED_D <= '0' when number = 0 else '0' when number = 1 else '1' when number = 2 else '1' when number = 3 else '1' when number = 4 else '1' when number = 5 else '1'; LED_E <= '0' when number = 0 else '0' when number = 1 else '1' when number = 2 else '1' when number = 3 else '1' when number = 4 else '1' when number = 5 else '1'; LED_F <= '0' when number = 0 else '0' when number = 1 else '0' when number = 2 else '0' when number = 3 else '0' when number = 4 else '1' when number = 5 else '1'; LED_G <= '0' when number = 0 else '0' when number = 1 else '0' when number = 2 else '0' when number = 3 else '0' when number = 4 else '1' when number = 5 else '1'; end rtl;